From 40bf68bbe0bdba305fde4ab825a06c085ba486fc Mon Sep 17 00:00:00 2001
From: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date: Wed, 16 Dec 2020 12:53:56 -0800
Subject: [PATCH] gcc: xtensa: add optimizations for shift operations

2020-12-16  Takayuki 'January June' Suwa  <jjsuwa_sys3175@yahoo.co.jp>
gcc/
	* config/xtensa/xtensa.md (*ashlsi3_1, *ashlsi3_3x, *ashrsi3_3x)
	(*lshrsi3_3x): New patterns.

gcc/testsuite/
	* gcc.target/xtensa/shifts.c: New test.
---
 gcc/config/xtensa/xtensa.md              | 43 ++++++++++++++++++++++++
 gcc/testsuite/gcc.target/xtensa/shifts.c | 31 +++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/xtensa/shifts.c

diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 5fbe4ad4af9f..462a7244a35d 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1071,6 +1071,16 @@
   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 })
 
+(define_insn "*ashlsi3_1"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(ashift:SI (match_operand:SI 1 "register_operand" "r")
+		   (const_int 1)))]
+  "TARGET_DENSITY"
+  "add.n\t%0, %1, %1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"2")])
+
 (define_insn "ashlsi3_internal"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
 	(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1083,6 +1093,17 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
 
+(define_insn "*ashlsi3_3x"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(ashift:SI (match_operand:SI 1 "register_operand" "r")
+		   (ashift:SI (match_operand:SI 2 "register_operand" "r")
+			      (const_int 3))))]
+  ""
+  "ssa8b\t%2\;sll\t%0, %1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"6")])
+
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1095,6 +1116,17 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
 
+(define_insn "*ashrsi3_3x"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
+		     (ashift:SI (match_operand:SI 2 "register_operand" "r")
+				(const_int 3))))]
+  ""
+  "ssa8l\t%2\;sra\t%0, %1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"6")])
+
 (define_insn "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
@@ -1114,6 +1146,17 @@
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
 
+(define_insn "*lshrsi3_3x"
+  [(set (match_operand:SI 0 "register_operand" "=a")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+		     (ashift:SI (match_operand:SI 2 "register_operand" "r")
+				(const_int 3))))]
+  ""
+  "ssa8l\t%2\;srl\t%0, %1"
+  [(set_attr "type"	"arith")
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"6")])
+
 (define_insn "rotlsi3"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
 	(rotate:SI (match_operand:SI 1 "register_operand" "r,r")
diff --git a/gcc/testsuite/gcc.target/xtensa/shifts.c b/gcc/testsuite/gcc.target/xtensa/shifts.c
new file mode 100644
index 000000000000..8d7e4a928d3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/xtensa/shifts.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+int lshift1(int v)
+{
+  return v << 1;
+}
+
+int lshift2(int v, int s)
+{
+  return v << (s * 8);
+}
+
+unsigned int lshift3(unsigned int v, int s)
+{
+  return v << (s * 8);
+}
+
+int rshift1(int v, int s)
+{
+  return v >> (s * 8);
+}
+
+unsigned int rshift2(unsigned int v, int s)
+{
+  return v >> (s * 8);
+}
+
+/* { dg-final { scan-assembler-not "slli" } } */
+/* { dg-final { scan-assembler-times "ssa8l" 2 } } */
+/* { dg-final { scan-assembler-times "ssa8b" 2 } } */